LOCKSVTAIRCR=Unlocked, LOCKSAU=Unlocked, LOCKNSMPU=Unlocked, LOCKNSVTOR=Unlocked, LOCKSMPU=Unlocked
Configure bits to lock down CPU features at runtime
| LOCKSVTAIRCR | Write ‘1’ to prevent updating the secure interrupt configuration until the next reset 0 (Unlocked): These registers can be updated 1 (Locked): Disables writes to the VTOR_S, AIRCR.PRIS, and AIRCR.BFHFNMINS registers |
| LOCKNSVTOR | Write ‘1’ to prevent updating the non-secure vector table base address until the next reset 0 (Unlocked): The address of the non-secure vector table can be updated 1 (Locked): The address of the non-secure vector table is locked |
| LOCKSMPU | Write ‘1’ to prevent updating the secure MPU regions until the next reset 0 (Unlocked): These registers can be updated 1 (Locked): Disables writes to the MPU_CTRL, MPU_RNR, MPU_RBAR, MPU_RLAR, MPU_RBAR_An and MPU_RLAR_An from software or from a debug agent connected to the processor in Secure state |
| LOCKNSMPU | Write ‘1’ to prevent updating the Non-secure MPU regions until the next reset 0 (Unlocked): These registers can be updated 1 (Locked): Disables writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn from software or from a debug agent connected to the processor |
| LOCKSAU | Write ‘1’ to prevent updating the secure SAU regions until the next reset 0 (Unlocked): These registers can be updated 1 (Locked): Disables writes to the SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers from software or from a debug agent connected to the processor |